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1 of 18 050907 general description the ds2704 provides 12 80 bits of eeprom data storage and a secure hash algorithm (sha) engine. the dallas 1-wire ? interface enables serial communication on a single battery contact and the 64-bit unique serial number allows multidrop networking and identification of individual devices. the 1280-bit memory is organized as 5 pages of 32 bytes each and supports storage of battery cell characteristics, charging voltage, current, and temperature parameters, as well as battery pack manufacturing data. the eeprom pages are in circuit rewritable and can be individually locked to write protect data. the ds2704 employs the secure hash algorithm (sha-1) specified in the federal information publication 180-1 and 180-2, and iso/iec 10118-3. sha-1 provides a robust cryptographic solution to ensure battery packs or other peripherals have been manufactured by authoriz ed sources. the ds2704 processes a host transmitted challenge and the 64- bit secret key stored on chip to produce a 160-bit response for transmission back to the host. the secret key is never transmitted between the battery and the host. application example pin configuration 3mm 3mm tdfn (top view ? pads on bottom) applications 2.5g/3g wireless handsets pdas handheld or notebook computers and terminals digital still and video cameras features ? secure challenge and response authentication using the sha-1 algorithm ? five lockable 32-byte pages of eeprom ? dallas 1-wire interface with standard and overdrive communications speeds ? unique 64-bit serial number ? compatible with ds2502 memory map and read function command ? operates with v dd as low as 2.5v ? tiny chip-scale ucsp and 3mm x 3mm tdfn packaging (pb-free) ordering information part temp range pin-package ds2704g+ -30 c to +85 c 3mm x 3mm tdfn-6 ds2704g+t&r -30 c to +85 c ds2704g+ on tape-and-reel ds2704w -30 c to +85 c bare die + denotes lead-free package. 1-wire is a registered trademark of dallas semiconductor. ds2704 1280-bit eeprom with sha-1 authentication www.maxim-ic.com downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 2 of 18 absolute maximum ratings voltage range on all pins, relative to v ss -0.3v to +6v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/je dec j-std-020a specification stresses beyond those listed under absolute maximum ratings may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rati ng conditions for extended peri ods may affect device. recommended dc op erating conditions (2.5v v dd 5.5v, t a = -30c to +85c.) parameter symbol conditions min typ max units supply voltage v dd (note 1) 2.5 5.5 v data pin dq (note 1) -0.3 +5.5 v dc electrical characteristics (2.5v v dd 5.5v, t a = -30c to +85c, typical values at v dd = 3.7v and t a = 25c.) parameter symbol conditions min typ max units standby mode (note 4) 1 3 a i dd0 -30c t a 70c standby mode (note 4) 1 2 a communication mode using standard bus timing (note 5) 5 25 a i dd1 communication mode using overdrive bus timing (note 5) 25 75 a i dd2 computation mode 75 500 a active current i ddp programming mode 400 750 a input logic high: dq v ih (note 1) 1.5 v input logic low: dq v il (note 1) 0.6 v output logic low: dq v ol i ol = 4ma (note 1) 0.4 v pull-down current: dq i pd 1 3 a eeprom reliability specification (2.5v v dd 5.5v, t a = -30 c to +85 c.) parameter symbol conditions min typ max units write endurance: eeprom data field n eec1 (note 2) 50,000 writes write endurance: secret eeprom n eec2 (note 2) 1,000 writes storage t ees (note 2, 3) 10 years ac electrical characteristics (2.5v v dd 5.5v, t a = -30c to +85c.) parameter symbol conditions min typ max units computation time t sha 30 ms eeprom copy time t eec (note 2) 10 ms downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 3 of 18 ac electrical characterist ics: 1-wire interface (2.5v v dd 5.5v, t a = -30 c to +85 c.) parameter symbol conditions min typ max units standard bus timing time slot t slot 60 120 s recovery time t rec 1 s write 0 low time t low0 60 120 s write 1 low time t low1 1 15 s read data valid t rdv 15 s reset time high t rsth 480 s reset time low t rstl 480 960 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s overdrive bus timing time slot t slot 6 16 s recovery time t rec 1 s write 0 low time t low0 6 16 s write 1 low time t low1 1 2 s read data valid t rdv 2 s reset time high t rsth 48 s reset time low t rstl 48 80 s presence detect high t pdh 2 6 s presence detect low t pdl 8 24 s dq capacitance c dq 60 pf note 1: all voltages are referenced to v ss . note 2: eeprom programming temperature range limited to 0 c to 50 c. note 3: device written n eec times then stored for t ees at 50 c. note 4: dq = v dd . note 5: current measured with minimum bus timing while the master issues: 1-wire reset, skip rom, write challenge, write repeated 0s until end of measurement. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 4 of 18 pin description pin symbol function 6 dq serial interface data i/o pin. bi-directi onal data transmit and receive at 16kbps or 143kbps. 5 v ss supply gnd and reference for se rial communication. attach v ss to battery pack negative terminal. 1 v dd supply input. bypass to v ss with 0.01 f typical. 2, 3, 4 nc no connection figure 1. block diagram detailed description the ds2704 is comprised of an eeprom memory array and sha-1 authenticat ion function that are accessed via a 1-wire interface. the 1-wire interface controls access by a host system to the 64- bit net address (rom id), sha-1 authentication, 1280-bit eeprom memory and eeprom status. the ds2704 operates in one of four modes: standby , communication, computation and programming. standby mode is the default mode of operation. whenever any task has been completed, the ic w ill automatically return to standby mode. standby mode is also directly entered if dq is low for a period of t rstl . once standby mode has been entered, dq can be returned to logic high and standby mode is retained. most operations are performed in communication mode, with the host system addr essing the ds2704 using net address commands and then retrieving eeprom and status data using memory func tion commands or setting up an authenticat ion exchange and retrieving the results. the supply current, i dd1 , varies depending on bus activity, communication direction, and selection of standard or overdrive bus timing. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 5 of 18 in sha-1 computation mode, the supply current increases to i dd2 for a period of t sha . the computation mode load current occurs after the last bit of one of the compute mac function commands is sent. programming mode is entered when writing the nonvolatile memory portions of the ds2704. the supply current increases to i ddp for t eec when a copy scratchpad, write status, comput e secret, clear/lock secret or clear/set overdrive timing command is executed. functional compatibility has been maintained betw een the ds2502 and ds2704 at the net address/rom command and function command levels for reading the memo ry and status data fields. since the ds2704 is based on eeprom technology versus the eprom technol ogy used for the ds2502, writing of the memory and status data fields is not the same as the ds2502. the ds2704 includes an on-chip charge pump to facilitate in- circuit programming. the need to apply an external high vo ltage programming pulse during pack manufacture is therefore eliminated. data can be written to a 0 or 1 value up to n eec times in the ds2704. the ability to reprogram the data in the eeprom pages makes the page address redirection bytes in the status data field unnecessary. therefore, the ds2704 maintains them for ds2502 read com patibility but they cannot be modified from their factory default values of ffh. authentication authentication is performed using a fips-180 compliant sha-1 one way hash algorithm on a 512-bit message block. the message block consists of a 64-bit secret, a 64-bit challenge and 384 bits of constant data. optionally, the 64-bit net address replaces 64 of the 384 bits of constant data us ed in the hash operation. contact dallas/maxim for details of t he message block organization. the host and the ds2704 both calculate the result based on the mutually known secret. the result data, known as the message authentication code (mac) or message diges t, is returned by the ds2704 for comparison to the hosts result. note that the secret is never transmitted on the bus and thus cannot be captured by observing bus traffic. each authentication attempt is initiated by the ho st system by providing a 64-bit random challenge via the write challenge command. the host then issues the compute mac or compute mac with rom id command. the mac is computed per fips 180, and then returned as a 160- bit serial stream, beginning with the least significant bit. ds2704 authentication commands write challenge [0ch]. this command writes the 64-bit challenge to the ds2704. the lsb of the 64-bit data argument can begin immediately after the msb of the command has been completed. if more than 8 bytes are written, the final value in the challenge register will be indeterminate. the write challenge command must be issued prior to every compute mac or compute next secret command for reliable results. compute mac without rom id [36h]. this command initiates a sha-1 computation based on the challenge value and internal secret. logical 1s are loaded in place of the rom id. this command allows the use of a master secret and mac response independent of the rom id. the ds2704 computes the mac in t sha after receiving the last bit of this command. after the mac computation is complete, the host must write 8 write zero time slots and then issue 160 read time slots to receive the 20-by te mac. see figure 7 on page 18 for command timing. compute mac with rom id [35h]. this command is structured the same as the compute mac without rom id, except that the rom id is included in the message block. with the rom id unique to each ds2704 included in the mac computation, use of a unique secr et in each token and a master secret in the host device is allowed. see application note white paper 4, available at http://www.maxim-ic.com , for more information. see figure 7 on page 18 for command timing. note : immediately after power-up, a du mmy compute mac command is required to initialize the ds2704. if the dummy command is not issued, the first authentication atte mpt is computed using a challenge value of 0. when issuing the dummy compute mac command, the command se quence can be terminated immediately following the 8 th bit of the compute mac command byte. waiting for t he sha-1 computation and reading the results back are not required. sha-1 related commands used while authenticating a battery or peripheral device are summarized in table 1 for convenience. four additional commands for clearing, comput ing and locking of the secret are described in detail in the following section. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 6 of 18 table 1. authentication function commands command hex function write challenge 0c writes 64-bit challenge for sha-1 processing. required prior to issuing compute mac and compute next secret commands. compute mac without rom id and return mac 36 computes hash the message block with logical 1s in place of the rom id. returns the 160-bit mac. compute mac with rom id and return mac 35 computes hash of the message block including the rom id. returns the 160-bit mac. secret management function commands clear secret [5ah]. this command sets the 64-bit secret to all 0s (0000 0000 0000 0000h). the host must wait t eec for the ds2704 to write the ne w secret value to eeprom. see fi gure 10 on page 20 for command timing. compute next secret without rom id [30h]. this command initiates a sha-1 computation of the mac and uses a portion of the resulting mac as the next or new secret. the mac computation is performed with the current 64-bit secret and the 64-bit challenge. logical 1s are loaded in place of the rom id. 64-bits of the output mac are used as the new secret value. the host must allow t sha after issuing this command for the sha calculation to complete, then wait t eec for the ds2704 to write the new secr et value to eeprom. see figure 8 on page 19 for command timing. compute next secret with rom id [33h]. this command initiates a sha-1 computation of the mac and uses a portion of the resulting mac as the next or new se cret. the mac computation is performed with the current 64-bit secret, the 64-bit rom id and the 64-bit challenge. 64-bits of the output mac are used as the new secret value. the host must allow t sha after issuing this command for the sha calculation to complete, then wait t eec for the ds2704 to write the new secret value to eepr om. see figure 8 on page 19 for command timing. lock secret [6ah]. this command write protects the 64-bit secret to prevent accidental or malicious overwrite of the secret value. the secret value stored in eeprom becomes "final." the host must wait t eec for the ds2704 to write the lock secret bit to eeprom. see figure 10 on page 20 for command timing. table 2. secret loading function commands command hex function clear secret 5a clears the 64-bit secret to 0000 0000 0000 0000h compute next secret without rom id 30 generates new global secret compute next secret with rom id 33 generates new unique secret lock secret 6a sets lock bit to prevent changes to the secret 1-wire speed control function commands clear overdrive [8dh]. this command selects the standard 1-wire timings shown in the electrical characteristics table. the setting is stored in eeprom so that the progra mmed speed selection can be recalled on initial power up. the host must wait t eec for the ds2704 to write the eeprom. see figure 10 for command timing. standard 1-wire timing is the factory default. set overdrive [8bh]. this command selects the overdrive 1-wi re timings shown in the electrical characteristics table. the setting is stored in eeprom so that the progra mmed speed selection can be recalled on initial power up. the host must wait t eec for the ds2704 to write the eeprom. see figure 10 for command timing. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 7 of 18 table 3. 1-wire speed control function commands command hex function set overdrive 8b sets 1-wire in terface timings to overdrive. clear overdrive 8d sets 1-wire interface timings to standard. (factory default) eeprom memory the ds2704 has a linear address space for access to the eeprom da ta field. the read memory and read data/generate crc memory function co mmands provide ds2502 legacy read access to the lower 1024 bits of the eeprom data field. read access to the entire eeprom data field is provided by the read all function command. the write scratchpad, read scratchpad and copy scratc hpad function commands provide write access to the eeprom data field. the eeprom memory is organized as 5 pages of 32 bytes each as shown in table 4. eeprom data field. all pages are read and write (r/w) accessible. when re ceived from the factory, the entire 1280-bit eeprom data field appears as logical 1s. table 4. eeprom data field address (hex) description read/write 0000 C 001f page 0 (32 bytes) r/w* 0020 C 003f page 1 (32 bytes) r/w* 0040 C 005f page 2 (32 bytes) r/w* 0060 C 007f page 3 (32 bytes) r/w* 0080 C 009f page 4 (32 bytes) r/w* 00a0 C ffff reserved * writing requires programming delay of t eec read memory [f0h]. the read memory command is used to read data from the lower 1024 bits (page 0 to page 3) of the 1280-bit eeprom data field. the bus ma ster follows the command by te with a 2-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indica tes a starting byte location within the data field. an 8-bit crc of the command byte and address bytes is computed by the ds2704 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc is deemed to be incorrect by the bus master, a reset pulse should be issued and the entire sequ ence repeated. if the crc is deemed to be correct by the bus master, read time slots can be issued to receive data from the eeprom data field starting at the initial address. the bus master can issue a rese t pulse at any point or continue to is sue read time slots until the end of page 3 of the data field is reached. if reading continues through the end of page 3, the bus master can issue eight additional read time slots and the ds2704 will respond with a 8-bit crc of all data bytes read fr om the initial starting byte through the last byte of page 3. terminating the command transaction with a reset pulse prior to reaching the end of page 3 results in a loss of availability of the 8-bit crc. read data/generate 8-bit crc [c3h] the read data/generate 8-bit crc command is used to read data from the lower 1024 bits (page 0 to page 3) of the 1280-bit eeprom data field. the bus master follows the command byte with a 2-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indica tes a starting byte location within the data field. an 8-bit crc of the command byte and address bytes is computed by the ds2704 and read back by the bus master to confirm that the correct command word and starting address were received. if the crc is deemed to be incorrect by the bus master, a reset pulse should be issued and the entire sequ ence repeated. if the crc is deemed to be correct by the bus master, read time slots can be issued to receive data from the eeprom data field starting at the initial address. the bus master can issue a rese t pulse at any point or continue to is sue read time slots until the end of downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 8 of 18 the 32-byte page is reached. if reading occurs through the end of the 32-byte page, the bus master can issue eight additional read time slots and the ds2704 will respond with a 8-bit crc of all data bytes read from the initial starting byte through the last byte of the current page. after the crc is received, additional read time slots return data starting with the first byte of the next page. this sequence will continue until the bus master reads page 3 and its accompanying crc. thus each page of data can be c onsidered to be 33 bytes long: the 32 bytes of user- programmed eeprom data and an 8-bit crc that gets generated autom atically at the end of each page. the read data/generate 8-bit crc command sequence can be exited at any point by issuing a reset pulse. read all [65h]. the read all command is used to read data from all 1280 bits (page 0 C page 4) of the eeprom data field. this includes page 0 C page 3 which are accessible via the ds2502 read memory and read data/gen crc legacy commands and page 4 which is only accessible using the read all command. the bus master follows the command byte with a 2-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8-bit crc of the command byte and a ddress bytes is computed by the ds2704. the bus master must issue 8 read time slots to receive the crc value, and then issue additional read time slots to receive data from the ds2704 starting at ta2:ta1. when reading begins within the eeprom data field (000 0h C 009fh) and continues past 009fh, an 8-bit crc of all data returned is computed by the ds2704 and returned fo llowing the last byte of the data field. if reading begins in the reserved range or time slots are issued after re ceiving the 8-bit crc, the ds2704 returns logical 1s. write scratchpad [6ch]. the write scratchpad command is used to write up to 8 bytes to the scratchpad buffer which is in turn used to program 1280-bit eeprom data field via the copy scratchpad command. the bus master issues the write scratchpad function command followed by a 1-byte addres s argument that depicts the starting byte position in the scratchpad of the following byte stream to be written. the valid range for the address is 00h C 07h. the address is auto-incremented after each data byte is written. when the address is greater than 07h, no further bytes will be accepted. inco mplete bytes are not written to t he scratchpad. the write scratchpad command fills the scratchpad lsbyte first, so when fewer than 8 bytes are written, the upper bytes of the scratchpad buffer contain data from previous operations. since the copy scratchpad command transfers the entire scratchpad to the eeprom data field, in complete writing of th e scratchpad should be d one with caution. if the master determines the scratchpad data is unsuitable to copy to the eeprom , the entire write sequence (command and data) must be repeated after issuing a reset pulse. read scratchpad [69h]. the read scratchpad command is used to re turn scratchpad data if verification of the scratchpad data is required prior to programming the eeprom data field. the bus master issues the read scratchpad function command followed by a 1-byte address ar gument that depicts the starting byte position in the scratchpad of the first byte to be read. the valid range for the address is 00h C 07h. the address is auto- incremented after each data byte is read. when the address is greater than 07h, any further reads will return bit values of 1. the ds2704 returns up to 64 bits from the scratchpad beginning with the least significant bit of the least significant byte. copy scratchpad [48h] . the copy scratchpad function command is used to transfer data from the 8-byte scratchpad buffer to the eeprom data field memory. transfers are aligned on 8-byte bou ndaries. the bus master issues the copy scratchpad function command follow ed by the 2-byte target address (ta1=(t7:t0), ta2=(t15:t8)). the ds2704 aligns target addresses to t he least significant byte (lsbyte) of each eight byte boundary by zeroing the three least significant bits of ta1. that is, ta1[t2:t0] are set internally to 000b. as an example, issuing the copy scratchpad command with ta 2:ta1 = 0x0020 or ta2:ta1 = 0x0027 results in the same 8-byte block being copied to page 1 beginning at address 0x0020. a delay of t eec is required to program the scra tchpad contents to the eeprom array. see figure 9 for command timing. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 9 of 18 eeprom status the ds2704 has a separate 8-byte li near address space for acce ss to the eeprom status data field using the read status and write status function commands. read status [aah]. the read status command is used to read data from the eeprom stat us data field. the bus master follows the command byte with a 2-byte addres s (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8-bit crc of the command byte and address bytes is computed by the ds2704 and read back by the bus master to confirm t hat the correct command word and starting address were received. if the crc is deemed to be incorrect by the bus master, a reset pulse should be issued and the entire sequence repeated. if the crc is deemed to be correct by the bus master, read time sl ots can be issued to receive data starting at the initial address. t he bus master can issue a reset pulse at any point or continue to issue read time slots until the end of the eeprom status data field is reached. if reading occurs through the end of the eeprom status data field, the bus master can issue ei ght additional read time slots and the ds2704 will respond with a 8-bit crc of all data bytes read from the initial star ting byte through the last byte. additional read time slots return logical 1s. the read status command sequence can be ended at any point by issuing a reset pulse. table 5. eeprom status field address (hex) description read/write 0000 write protect page bits b0: page 0 write protect b1: page 1 write protect b2: page 2 write protect b3: page 3 write protect b4: page 4 write protect b5: reserved for tmex b6: reserved for tmex b7: reserved for tmex r/w* 0001 factory programmed to ffh r 0002 factory programmed to ffh r 0003 factory programmed to ffh r 0004 factory programmed to ffh r 0005-0006 reserved r 0007 factory programmed to 00h r * one time write to 0 write status [55h] the write status command is used to program the eeprom st atus data field. only the write protect page bits at address 0000h are writable. the other bytes are factory programmed to the values in table 5. the write protect page bits are set to logical 1s when received from th e factory. eeprom page data can be programmed multiple times until its associated write protect page bit is progra mmed to a logical 0. once a write protect page bit is programmed to a logical 0, it cannot be programmed back to a logical 1. programming a write protect page bit to a logical 0 prevents any future modification or overwriting of the data in the associated page. to protect page data from modification, the bus master wr ites the write status function command followed by one byte of status data containing the write protect page bits (b7:b0). the stat us data must be written least significant bit to most significant bit, that is b0 to b7. once the eight h bit of the status data is completed, the write operation cannot be undone. if the write operation is abandoned prio r to completing the status data byte, the entire write sequence must be repeated after issuing a reset pulse. after the programming write delay (t eec ), the master can issue a read status function command to verify that the appropriate write protect page bits have been programmed. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 10 of 18 table 6. eeprom memory and status function commands command hex function read memory f0 read data from the lower 1024 bits of the 1280-bit eeprom memory data field. generates a crc value if read continues to end of the 4 th page. read data/generate crc c3 read data from lower 4 pages of the eeprom memory data field. generates a crc value of the data read from each page if read continues to the end of page. read all 65 read data from all 5 page s of the eeprom memory data field. read status aa read data from the 8-byte eeprom status data field. write status 55 write the page protection bits in the eeprom status data field. write scratchpad 6c write up to 8 bytes of data to the scratchpad register. read scratchpad 69 read up to 8 bytes of the scratchpad register data. copy scratchpad 48 programs the scratchpad data to eeprom data field at the target address ta2:ta1. note : the read data, read data/generate crc and read stat us commands filter the target address (ta2:ta1) value with a 007fh and mask that lim its the addressable size of the eeprom data field and eeprom status field to 1024 bits. target address values equal to or greater than 0080h (128 decimal) return data from the lower 128 bytes of the respective data field. it is also important to note that the filter is applied prior to calculation of the crc, so that target address values that are multiples of 128 return the same crc. the crc values should be considered correct only for ta2:ta1 = 0000h to 007fh. 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. a multidrop bus is a 1-wire bus with multiple slaves, while a single-drop bus has only one slave device. in all instan ces, the ds2704 is a slave device. the bus master is typi cally a microprocessor in the host system. the discussion of this bus system consists of five topics: 64-bit net address, crc generation, har dware configuration, transac tion sequence, and 1-wire signaling. 64-bit net address (rom id) each ds2704 has a unique, factory-programmed 1-wire ne t address that is 64 bits in length. the term net address is synonymous with the rom id or rom co de terms used in the ds2502 and other dallas 1-wire documentation. the first eight bits of the net address ar e the 1-wire family code (09h). the next 48 bits are a unique serial number. the last eight bi ts are a cyclic redundancy check (crc) of the first 56 bits (see figure 2). the 64-bit net address and the 1-wire i/o circuitry bu ilt into the device enable the ds2704 to communicate through the 1-wire protocol detailed in this data sheet. figure 2. 1-wire net address format 8-bit crc 48-bit serial number 8-bit family code (09h) msb lsb downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 11 of 18 crc generation the ds2704 has an 8-bit crc stored in the most significa nt byte of its 1-wire net address and generates a crc during some command protocols. to ensure error-free transmi ssion of the address, the host system can compute a crc value from the first 56 bits of the addres s and compare it to the crc from the ds2704. the host system is responsible for verifying the crc value and taking action as a result. the ds2704 does not compare crc values and does not prevent a command sequen ce from proceeding as a result of a crc mismatch. proper use of the crc can result in a communicati on channel with a very high level of integrity. the crc can be generated by the host using a circuit consis ting of a shift register and xor gates as shown in figure 3, or it can be generated in software using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire crc is available in application note 27: understanding and using cyclic redundancy checks with dallas semiconductor i button ? products ( www.maxim-ic.com/appnoteindex ). in the circuit in figure 3, the shift register bits are initialized to 0. then, star ting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. figure 3. 1-wire crc generation block diagram during some command sequences, the ds2704 also generates an 8-bit crc and provides this value to the bus master to facilitate validation for the transfer of command, addr ess, and data from the bus master to the ds2704. the ds2704 computes an 8-bit crc for the command and address bytes received from the bus master for the read memory, read status and read/generate crc commands to confirm that these bytes have been received correctly. the crc generator on the ds2704 is also used to provide verification of error-free data transfer as each eeprom page is sent to the master during a read data/g enerate crc command an d for the 8 bytes of information in the status memory field. in each case where a crc is used for data transfer validat ion, the bus master must ca lculate the crc value using the same polynomial function and compare the calculat ed value to the crc either stored in the ds2704 net address or computed by the ds2704. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry in the ds2704 that prevents the a command sequence from proceeding if the stored or calculated cr c from the ds2704 and the calculated crc from the host do not match. hardware configuration because the 1-wire bus has only a single line, it is importa nt that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must connect to the bus with open-drain or tri-state output drivers. the ds2704 uses an open-drain output driver as part of the bidirectional interface circuitry shown in figure 4. if a bidirectional pin is not available on the bus master, separate output and input pins can be connected together. the 1-wire bus must have a pullup resistor at the bus-master end of the bus. a value of between 2k and 5k is recommended. the idle state for the 1-wi re bus is high. if, for any reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. note that if the bus is left low for more than t rstl , slave devices on the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction. msb xor xor lsb xor input i button is a registered trademark of dallas semiconductor. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 12 of 18 figure 4. 1-wire bu s interface circuitry transaction sequence the protocol for accessing the ds2704 th rough the 1-wire port is as follows: ? initialization ? net address command ? function command(s) ? data transfer (not all commands have data transfer) all transactions of the 1-wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master, followed by a presence pulse simultaneously transmitted by the ds2704 and any other slaves on the bus. the presence pulse tells the bus master that one or more devices are on the bus and ready to operate. for more details, see the i/o signaling section below. net address commands once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. the name of each net address command (rom command) is followed by the 8-bit opcode for that command in square brackets. read net address [33h]. this command allows the bus master to read the ds2704s 1-wire net address. this command can only be used if there is a single slave on the bus. if more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). match net address [55h]. this command allows the bus master to specifically address one ds2704 on the 1-wire bus. only the addressed ds2704 responds to any subsequent function comm and. all other slave devices ignore the function command and wait for a reset pulse. this command can be used with one or more slave devices on the bus. skip net address [cch]. this command saves time when there is only one ds2704 on the bus by allowing the bus master to issue a function command without specifyi ng the address of the slave. if more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. search net address [f0h]. this command allows the bus master to use a process of elimination to identify the 1-wire net addresses of all slave devices on the bus. the search process involves the repetition of a simple three- step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple three-step routine on each bit location of the net address. after one complete pass through all 64 bits, the bus master knows the address of one dev ice. the remaining devices can then be identified on additional iterations of the pr ocess. see chapter 5 of the book of i button standards for a comprehensive discussion of a net address search , including an actual example ( www.maxim-ic.com/ibuttonbook ). downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 13 of 18 i/o signaling the 1-wire bus requires strict signaling protocols to ensure data integrity. the four protocols used by the ds2704 are as follows: the initialization sequence (reset pulse follo wed by presence pulse), writ e 0, write 1, and read data. the bus master initiates all these type s of signaling except the presence pulse. the initialization sequence required to begin any communication with the ds2704 is shown in figure 5. a presence pulse following a reset pulse indicates that the ds2704 is ready to accept a net address command. the bus master transmits (tx) a reset pulse for t rstl . the bus master then releases the line and goes into receive mode (rx). the 1-wire bus line is then pulled high by the pullup resistor. after detecting the rising edge on the dq pin, the ds2704 waits for t pdh and then transmits the presence pulse for t pdl . figure 5. 1-wire initialization sequence write-time slots a write-time slot is initiated when the bus master pulls the 1-wire bus from a logic-high (inactive) level to a logic-low level. there are two types of write-time slots: wr ite 1 and write 0. all write-time slots must be t slot in duration with a 1 s minimum recovery time, t rec , between cycles. the ds2704 samples the 1-wire bus line between t low1_max and t low0_min after the line falls. if the line is high when sampled, a write 1 occurs. if the line is low when sampled, a write 0 occurs. the sample window is illustrate d in figure 6. 1-wire write- and read-time slots. for the bus master to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line to be pulled high less than t rdv after the start of the write time slot. for the host to generate a write 0 time slot, the bus line must be pulled low and held low for the duration of the write-time slot. read-time slots a read-time slot is initiated when the bus master pulls the 1 -wire bus line from a logic-high level to a logic-low level. the bus master must keep the bus line low for at least 1 s and then release it to allow the ds2704 to present valid data. the bus master can then sample the data t rdv from the start of the read-t ime slot. by the end of the read- time slot, the ds2704 releases the bus line and allows it to be pulled high by the external pullup resistor. all read- time slots must be t slot in duration with a 1 s minimum recovery time, t rec , between cycles. see figure 6 and the timing specifications in the electrical ch aracteristics table for more information. t r s tl t pdl t r s th t pdh pack+ pack- line type legend: bus master active low ds2704 active low resistor pullup both bus master and ds2704 active low dq downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 14 of 18 figure 6. 1-wire write- and read-time slots downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 15 of 18 table 7. all function commands compatibility command hex function ds2502 ds2703 write challenge 0c writes 64-bit challenge for sha-1 processing. required prior to all compute mac and compute next secret commands. cc compute mac without rom id and return mac 36 computes hash of the message block with all 1s in place of the rom id. cc compute mac with rom id and return mac 35 computes hash of the message block using the rom id. cc clear secret 5a clears the 64-bit secret to 0000 0000 0000 0000h. compute next secret without rom id 30 generates new global secret. np compute next secret with rom id 33 generates new unique secret. np lock secret 6a sets lock bit to prevent changes to the secret. np read memory f0 read data from 1024-bit eeprom memory data field. cc read data/generate crc c3 read data from 1024-bit eeprom memory data field and generate a crc value of the data read during the operation. cc read all 65 read data from the all 5 pages of the eeprom memory data field. read status aa read data from the 8-byte eeprom status data field. cc write status 55 write data to the eeprom status data field. np write scratchpad 6c write data to the 8-byte scratchpad buffer. read scratchpad 69 read data from the 8-byte scratchpad buffer. copy scratchpad 48 write scratchpad data to eeprom data field. set overdrive 8b sets 1-wire interface timings to overdrive. np clear overdrive 8d sets 1-wire interface timings to standard. (factory default). np reset bb resets ds2704 (software por). cc key: cc ? complete compatibility, np ? no programming pulse required on ds2704. downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 16 of 18 table 8. guide to function command requirements command issue memory address issue 00h before read read/write time slots readback crc write challenge write: 64 compute mac yes read: up to 160 compute next secret clear/lock secret, set/clear overdrive read memory 16 bits: ta1, ta2 read: up to 1024 (data) up to 16 (crc) after cmd + ta2:ta1, end of page 3 read data/gen crc 16 bits: ta1, ta2 read: up to 1024 (data) up to 40 (crc) after cmd + ta2:ta1, end of each page read all 16 bits: ta1, ta2 read: up to 1280 (data) after cmd + ta2:ta1, end of page 4 read status 16 bits read: up to 64 (data) up to 16 (crc) after cmd + ta2:ta1, end of status field write status write: 8 write scratchpad 8 bits write: up to 64 read scratchpad 8 bits read: up to 64 copy scratchpad 16 bits: ta1, ta2 reset figure 7. compute mac function command downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 17 of 18 figure 8. compute next secret function command figure 9. copy scratchpad function command downloaded from: http:///
ds2704: 1280-bit eeprom with sha-1 authentication 18 of 18 figure 10. clear/lock secret, se t/clear overdrive function commands package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) downloaded from: http:///

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